Summary: How to create pure silicon crystals
How is it possible for the IC industry to continue to make such gains, and how do they build so many circuits on one chip anyway? In order for us to be able to understand this, we have to take a look at the monolithic fabrication process. Lith comes from the Greek word for stone, and mono means one, of course. Thus, monolithic construction refers to building the circuit in "one stone" or in one single crystal substrate.
In order for us to do this however, we first of all need the "stone", so let's see where that comes from.
We start out with a natural form of silicon which is
very abundant (and relatively pure); quartzite or
We have seen that on the order of
The silicon is crushed and reacted with
Many of the impurities in the silicon (aluminum, iron,
phosphorus, chromium, manganese, titanium, vanadium and carbon)
also react with the
Although the EGS is relatively pure, it is in a polycrystalline form which is not suitable for device manufacture. The next step in the process is to grow single crystal silicon which is usually done via the Czochralski(pronounced "cha-krawl-ski") method to make what is sometimes called CZ silicon. The Czochralski process involves melting the EGS in a crucible, and then inserting a seed crystal on a rod called a puller which is then slowly removed from the melt. If the temperature gradient of the melt is adjusted so that the melting/freezing temperature is just at the seed-melt interface, a continuous single crystal rod of silicon, called a boule, will grow as the puller is withdrawn.
Figure 1 is a diagram of how the Czochralski process works. The entire apparatus must be enclosed in an argon atmosphere to prevent oxygen from getting into the silicon. The rod and the crucible are rotated in opposite directions to minimize the effects of convection in the melt. The pull-rate, the rotation rate and the temperature gradient must all be carefully optimized for a particular wafer diameter and growth direction. The <111> direction (along a diagonal of the cubic lattice structure) is usually chosen for wafers to be used for bipolar devices, while the <100> direction (along one of the sides of the cube) is favored for MOS applications. Currently, wafers are typically 6" or 8" in diameter, although 12" diameter wafers (300 mm) are looming on the horizon.
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Once the boule is grown, it is ground down to a standard diameter (so the wafers can be used in automatic processing machines) and sliced into wafers, much like a salami. The wafers are etched and polished, and move on to the process line. A point to note however, is that due to "kerf" losses (the width of the saw blade) as well as polishing losses, more than half of the carefully grown, very pure, single crystal silicon is thrown away before the circuit fabrication process even begins!